Any serious radio transceiver employing PLL synthesis with VCO oscillators requires a high-precision frequency reference. An OCXO (Oven Controlled Crystal Oscillator) provides stability that is an order of magnitude better than ordinary crystal oscillators or TCXOs — and that is exactly what is needed when synthesisers such as the LMX2592, Si5341, or ADF4351 must generate clean and stable local oscillators for a superheterodyne receiver/transmitter.
This board is designed as the central 20 MHz reference clock source for the transciver project. Instead of giving each PLL synthesiser its own oscillator (with all the attendant isolation and coherency problems), a single precision OCXO distributes the reference signal to four independent outputs through a fast SiGe fanout buffer. This ensures phase coherence across all synthesisers in the system, and with it predictable behaviour of every conversion stage in the transceiver.
PCB: 4-Layer Design for Controlled Impedance
The printed circuit board measures 50 × 50 mm and is manufactured as a 4-layer PCB with a total thickness of 1.2 mm and an ENIG (Electroless Nickel Immersion Gold) surface finish. ENIG was chosen for reliable SMD soldering — the flat gold surface ensures consistent solder joints without the pad coplanarity problems that occur with HASL finishes.
The layer stackup follows the JLCPCB specification (JLC04161H-1080 stackup) for a 1.2 mm PCB:
| Layer | Material | Thickness | Notes |
|---|---|---|---|
| Top Layer | Copper (1 oz) | 0.035 mm | Signal layer + components |
| Prepreg | 1080 × 1 | 0.076 mm | εr = 3.91 |
| Inner Layer 2 | Copper (0.5 oz) | 0.015 mm | GND plane |
| Core | FR-4 | ~0.95 mm | εr = 4.6 |
| Inner Layer 3 | Copper (0.5 oz) | 0.015 mm | +3.3 V plane |
| Prepreg | 1080 × 1 | 0.076 mm | εr = 3.91 |
| Bottom Layer | Copper (1 oz) | 0.035 mm | Signal layer |
The key parameter for RF design is the distance from the top layer to the GND plane — that is the prepreg thickness of just 0.076 mm (76 µm). With the 1080 prepreg dielectric constant εr = 3.91, this allows 50-ohm microstrip traces on the top layer with a width of only 0.156 mm (≈ 6.1 mil). The GND pour on the top layer must be spaced between 0.5 mm and 0.8 mm from these traces to maintain impedance and avoid capacitive coupling.
The internal GND plane provides an uninterrupted return path for all signal traces, while the separate +3.3 V plane serves as a low-inductance power distribution layer. Ground stitching vias connecting the GND pour on the top/bottom layers to the internal GND plane provide additional shielding and reduce parasitic inductances.
Power Supply: Dual LT3045 Ultra-Low-Noise LDO Regulator
Power Architecture
The board is powered by an external regulated +5 V DC supply delivered through two 5-pin headers (J1 and J4) at the standard 2.54 mm (0.1″) pitch. On each header, two outer pins are GND and two are +5 V DC — the doubled pins reduce contact resistance and improve supply reliability. Standard 2.54 mm pin headers support up to 3.0 A per pin and a voltage rating of 250 V AC/DC, which is more than sufficient for this application. An additional GND path is provided through 4 mounting screws (H1–H4) that mechanically and electrically connect the board to the host board, further reducing the GND return path impedance.
Both pin headers must be connected — the system is designed for parallel operation of two LT3045 regulators, each capable of 500 mA, providing a combined capacity of 1 A on the shared 3.3 V output.
Series Input Resistors — Thermal Relief
Each of the two +5 V supply lines has a series resistor — R21 and R22, each 2.2 Ω in a 2512 package rated at 1.5 W. In parallel, they form an equivalent resistance of 1.1 Ω with a total dissipation capacity of 3 W. Their purpose is to reduce the voltage drop across the LT3045 regulators — without them, all power loss from the input-to-output voltage differential (5 V − 3.3 V = 1.7 V) would fall entirely on the IC packages, causing significant heating.
Calculation During OCXO Warm-Up (Worst Case)
During oven warm-up, the OCXO draws up to 600 mA, while the ADCLK944 buffer with its terminations consumes approximately 155 mA, giving a total load of about 755 mA:
- Voltage drop across R21 ∥ R22: V = I × R = 0.755 A × 1.1 Ω = 0.83 V
- Input voltage at LT3045: 5.0 V − 0.83 V = 4.17 V
- Dissipation in resistors: P = I² × R = 0.755² × 1.1 = 0.63 W (0.31 W per resistor — within the 1.5 W limit)
- Dissipation in LT3045 (both combined): P = (4.17 − 3.3) × 0.755 = 0.66 W (0.33 W per IC)
Calculation at Steady State
In steady-state operation the OCXO draws approximately 230 mA, and total load is about 390 mA:
- Voltage drop across R21 ∥ R22: V = 0.39 A × 1.1 Ω = 0.43 V
- Input voltage at LT3045: 5.0 V − 0.43 V = 4.57 V
- Dissipation in resistors: P = 0.39² × 1.1 = 0.17 W (0.08 W per resistor)
- Dissipation in LT3045 (both combined): P = (4.57 − 3.3) × 0.39 = 0.50 W (0.25 W per IC)
This approach offloads part of the thermal dissipation onto the resistors and relieves the LT3045 ICs, ensuring safe operation without forced cooling.
SET Pin — Output Voltage Programming
The LT3045 uses an internal precision 100 µA current source that flows through an external resistor connected between the SET pin and GND. The output voltage is defined by the formula:
VOUT = ISET × RSET = 100 µA × 16.5 kΩ = 3.3 V
Resistor R1 = 16.5 kΩ (0402 package) is selected with a tolerance of 0.1% (Vishay TNPW series) — this is a critical component because its accuracy directly determines the output voltage precision. With a resistor tolerance of 0.1% and SET current accuracy of ±1%, the total initial output voltage accuracy is approximately ±1.1%.
According to the datasheet, adding a capacitor between the SET pin and GND improves noise characteristics, PSRR (Power Supply Rejection Ratio), and transient response, at the cost of increased start-up time. The datasheet specifies a typical value of 0.47 µF for CSET. In this design, 4.7 µF (C9, X7R 1206) is used — 10 times the typical capacitance. The larger CSET capacitor forms a lower low-pass filter with the equivalent resistance of the SET pin (≈ RSET / open-loop gain), further suppressing reference current source noise at lower frequencies. The trade-off is a longer start-up time, but for an OCXO application where the oven warm-up already takes 3–5 minutes, this is not a concern. This is a justified modification that improves overall power supply noise in the passband of interest.
Output Phasing — Ballast Resistors
The outputs of both LT3045 regulators are connected through two 20 mΩ resistors (out#1 and out#2) to a common OCXO_VCC node. These resistors balance the currents between the paralleled regulators — without them, even a minimal output voltage difference would cause one regulator to carry the entire load.
On this board, these resistors are implemented as PCB traces with 1 oz (35 µm) copper thickness, 0.3 mm width, and 18 mm length each, in a meandered layout. The resistance of the copper trace is calculated as:
R = ρ × L / (w × t) = 1.724 × 10−8 × 0.018 / (0.3 × 10−3 × 35 × 10−6) ≈ 30 mΩ
The practical value is close to the 20 mΩ specification — the real conductivity of PCB copper and process tolerances yield an effective resistance in the 20–30 mΩ range, which is sufficient for reliable current sharing.
The voltage drop at steady-state load of ~195 mA per regulator is only V = 0.195 × 0.020 = 3.9 mV — completely negligible for power supply quality, yet sufficient for balancing the currents.
LED Indicators
Two amber LED indicators (D1 and D2 in 1206 packages) signal power supply health: D1 (5V OK) with ballast resistor R19 = 1 kΩ confirms the presence of input voltage, while D2 (3V3 OK) with resistor R20 = 470 Ω indicates proper 3.3 V regulated output.
OCXO: IQD LFOCXO094148
The heart of the board is the IQD LFOCXO094148 — a miniature OCXO in a package measuring just 7.5 × 5.5 mm (IQOV-116 series), making it one of the smallest SMD OCXOs on the market. This is a crystal oscillator with an actively regulated oven that maintains the crystal at a constant temperature, thereby eliminating the influence of ambient conditions on frequency.
Key Specifications
| Parameter | Value |
|---|---|
| Frequency | 20.000 MHz |
| Frequency stability | ±0.02 ppm (±20 ppb) over −40 °C to +85 °C |
| Output | HCMOS, 15 pF load |
| Supply voltage | 3.3 V |
| Current during warm-up | up to 600 mA (~3 minutes) |
| Current at steady state | ~230 mA @ 25 °C |
| Phase noise | < −150 dBc/Hz @ 1 kHz offset |
| Phase noise | < −152 dBc/Hz @ 10 kHz offset |
| Ageing | < ±500 ppb/year (typical) |
| Warm-up time | < 5 min to within ±100 ppb of final specification |
| Output duty cycle | 45/55% |
| Rise/fall time | ≤ 6 ns |
Shielding
The OCXO is protected by a Würth Elektronik WE-SHC SMD shield (SH1, P/N 36103166S) measuring 36 × 10 mm, which prevents radiation into adjacent circuits and protects against external interference. Beneath the shield there is also a WE-SHC shield SH3 (P/N 3670400, 36 × 7 mm) for additional isolation.
Series Resistor R2
Between the OCXO output and the buffer input there is a series resistor R2 = 22 Ω (1206). Its purpose is to dampen ringing on the signal trace — the somewhat longer PCB track between the OCXO and the buffer can act as a short transmission line where reflections manifest as overshoot and oscillation on the HCMOS signal edges.
For initial testing, R2 can be bypassed with a solder bridge (0 Ω jumper) to establish a baseline measurement, after which the optimal value is determined experimentally. A range of 10 Ω to 22 Ω is typical — a lower value has less impact on edge speed but provides weaker damping, while a higher value better suppresses reflections at the cost of slightly slower edges. For a 20 MHz signal, 22 Ω is a safe choice that does not degrade signal integrity.
Buffer: ADCLK944BCPZ-R7
The signal from the OCXO enters the Analog Devices ADCLK944BCPZ-R7 — an ultrafast fanout buffer fabricated on ADI’s proprietary XFCB3 silicon-germanium (SiGe) bipolar process. This IC accepts a single clock input and distributes it to four identical LVPECL outputs.
Key Specifications
| Parameter | Value |
|---|---|
| Maximum operating frequency | 7.0 GHz |
| Additive broadband random jitter | 50 fs RMS |
| Supply voltage (VCC − VEE) | 2.5 V to 3.3 V |
| Typical core consumption | ~75 mA @ 3.3 V |
| Input termination | 100 Ω differential (on-chip) |
| Output swing | 800 mV per side (1.6 V differential) |
| Package | 16-pin LFCSP (3 × 3 mm) |
An additive jitter of just 50 fs RMS means the buffer virtually does not degrade the quality of the reference signal — the total output jitter is dominantly determined by the quality of the OCXO source, not the buffer itself.
Input Configuration
The ADCLK944 receives the single-ended HCMOS signal from the OCXO on the CLK pin, while CLK (complementary input) is connected to the VREF pin which provides the appropriate DC bias for single-ended operation. The internal 100 Ω differential termination resistors with centre-tap (VT pin) ensure impedance matching. Bypass capacitors C10 (1 µF), C11 and C13 (100 nF NP0) filter noise on the supply and reference pins.
Phase Noise
The ADCLK944 phase noise is exceptionally low — when measured at 1 GHz with an Agilent E5052B analyser, the IC adds a negligible noise contribution, typically below −155 dBc/Hz at 10 kHz offset. For a 20 MHz reference signal, the additive phase noise of the buffer is far below the noise of the OCXO itself, so the OCXO remains the dominant source of phase noise in the system.
Output Terminations: Thévenin 50 Ω to VCC − 2 V
Each of the four LVPECL outputs of the ADCLK944 (Q0/Q0, Q1/Q1, Q2/Q2, Q3/Q3) requires termination to VCC − 2 V (3.3 V − 2.0 V = 1.3 V). According to the datasheet, the output stages are emitter-follower LVPECL drivers that require 50 Ω to 1.3 V (VCC minus 2 V) for each side of the differential pair.
Instead of using a separate 1.3 V supply, the practical solution is a Thévenin equivalent with two resistors:
- Rhigh = 130 Ω to VCC (+3.3 V)
- Rlow = 82 Ω to GND
Thévenin equivalent resistance: RTH = 130 ∥ 82 = (130 × 82) / (130 + 82) = 10,660 / 212 ≈ 50.3 Ω ✓
Thévenin equivalent voltage: VTH = 3.3 × 82 / (130 + 82) = 3.3 × 82 / 212 ≈ 1.28 V ≈ VCC − 2 V ✓
This configuration uses 8 × 130 Ω (R3, R8–R12, R15, R17) and 8 × 82 Ω (R4–R7, R13, R14, R16, R18) resistors in 1206 packages — two resistors per output line, 16 resistors total for 4 differential outputs.
Average current through each termination network: approximately 10 mA from VCC per single-ended line, which for 8 lines (4 × differential) gives approximately 80 mA total termination power consumption from the 3.3 V supply.
Outputs: 4 × MMCX Connectors
The signal from the terminated LVPECL outputs reaches four MMCX female connectors (J5, J6, J7, J8 — Molex 73415-1471) mounted vertically on the PCB. Each output is DC-decoupled through a 100 nF NP0 capacitor (C22, C23, C24, C25 in 1206 packages) that blocks the DC component of the LVPECL signal and passes only the AC signal to the PLL synthesisers.
Signal Level and Matching
The ADCLK944 LVPECL output has a swing of ±400 mV around the DC operating point, which after AC coupling produces approximately 800 mVpp differential or 400 mVpp single-ended signal at the connector. Depending on the input requirements of each PLL (LMX2592, Si5341, ADF4351), the signal level may need adjustment — in that case a π-attenuator is added on the receiving side for precise attenuation before entering the PLL VCO reference input.
Cabling
The recommended connection method is via pre-made PTFE coaxial cables (RG-178) of 5–10 cm length with MMCX male connectors on both ends. RG-178 has a characteristic impedance of 50 Ω, a PTFE dielectric for low loss, and is flexible enough for internal mounting inside a transceiver enclosure. Short cable lengths (< 10 cm) ensure negligible signal loss at 20 MHz — RG-178 loss is on the order of 0.3 dB/m at 100 MHz, so at 10 cm and 20 MHz it is virtually zero.
Total System Power Consumption
| Consumer | Steady State | Warm-Up |
|---|---|---|
| OCXO (IQD LFOCXO094148) | ~230 mA | ~600 mA |
| ADCLK944 (core) | ~75 mA | ~75 mA |
| Terminations (8 × Thévenin) | ~80 mA | ~80 mA |
| LT3045 × 2 (quiescent) | ~5 mA | ~5 mA |
| LED indicators | ~5 mA | ~5 mA |
| Total from 3.3 V | ~395 mA | ~765 mA |
| Total from 5 V input | ~400 mA | ~770 mA |
Passive Components and Design Philosophy
Most passive components are in 1206 packages — deliberately chosen instead of smaller 0402/0603 sizes for easier hand soldering and greater solder joint reliability. The exception is R1 (16.5 kΩ SET resistor) in a 0402 package — the only precision component where the smaller size is not a problem since it carries negligible current, and the 0402 package is required because the Vishay TNPW series 0.1% resistor in this value comes in that format.
All bypass capacitors (C11–C15, C18–C25) are 100 nF NP0/C0G dielectric — chosen over cheaper X7R specifically for the temperature stability and linearity of NP0 ceramics. In a reference clock distribution system, any non-linearity in a bypass capacitor can modulate the supply and introduce phase noise. NP0 capacitors have no piezoelectric effect and maintain constant capacitance regardless of applied DC voltage, making them ideal for low-noise power supplies.
Bill of Materials — Cost Overview
The total cost of electronic components (Mouser, single quantity) is approximately €100 excluding connectors MMCX which are usually available at better prices for lot packages on AliExpress, VAT, and shipping. The most expensive item is the OCXO itself (~€39.67), followed by the two LT3045HMSE units (~€23.46) and the ADCLK944 (~€10.71). The remaining passive components represent a relatively small share of the total cost.
Conclusion
The OCXO 20 MHz Source Board is a compact and carefully designed module that provides a high-quality reference frequency for the entire transceiver system. The combination of the IQD OCXO with ±20 ppb stability, ultra-low-noise dual LT3045 power supply, and SiGe ADCLK944 buffer with 50 fs additive jitter yields a reference source that does not degrade the performance of even the most demanding PLL synthesisers.
Four independent MMCX outputs allow clock distribution to the LMX2592 (potential VHF/UHF/SHF synthesis), Si5341 (various IF clock generation), ADF4351 (potential HF and VHF synthesiser), and one spare channel — all with phase coherence from a single source. The signal level at each output should be adjusted for the specific PLL using a π-attenuator on the receiving side, and connections are best made with PTFE RG-178 cables of 5–10 cm length with MMCX connectors.
The 50 × 50 mm PCB mounts to the host board with screws that also serve as additional GND contacts, while the compact dimensions and SMD construction allow integration into any transceiver module.
9A6KX — February 2026.